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Agilent HDMP-0452 Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops
Data Sheet
Description The HDMP-0452 is a Quad Port Bypass Circuit (PBC) with a Clock and Data Recovery (CDR) circuit included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system. A Port Bypass Circuit (PBC) consists of multiple 2:1 multiplexers daisy chained along with a CDR. Each port has two modes of operation: "disk in loop" and "disk bypassed". When the "disk in loop" mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0452's TO_NODE[n] differential output pins to the Disk Drive Transceiver IC's (e.g., an HDMP-1536A) Rx differential input pins. Data from the Disk Drive
Transceiver IC's Tx differential outputs goes to the HDMP-0452's FM_NODE[n] differential input pins. Figures 3 and 4 show connection diagrams for disk drive array applications. When the "disk bypassed" mode is selected, the disk drive is either absent or nonfunctional and the loop bypasses the hard disk. The "disk bypassed" mode is enabled by pulling the BYPASS[n]- pin low. Leave BYPASS[n]- floating to enable the "disk in loop" mode. HDMP0452s may be cascaded with other members of the HDMP-04XX/ HDMP-05XX family through the FM_LOOP and TO_LOOP pins to accommodate any number of hard disks. See Table 2 to identify which of the 5 cells (0:4) will provide FM_LOOP and TO_LOOP pins (cable connections). The unused cells in this PBC may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells.
Features * Supports 1.0625 GBd fibre channel operation * Supports 1.25 GBd Gigabit Ethernet (GE) operation * Quad PBC/CDR in one package * CDR location determined by choice of cable input/output * Valid amplitude detection on FM_NODE[0] input * Equalizers on all inputs * High speed LVPECL I/O * Buffered Line Logic (BLL) outputs (no external bias resistors required) * 0.66 W typical power at VCC = 3.3 V * 44 pin, 10 mm, low cost plastic QFP package Applications * RAID, JBOD, BTS cabinets * 1 => 1-4 serial buffer with or w/o CDR
HDMP-0452
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by Electrostatic Discharge (ESD).
An HDMP-0452 may also be used as five 1:1 buffers, one with a CDR and four without. For example, an HDMP-0452 may be placed in front of a CMOS ASIC to clean the jitter of the outgoing signal (CDR path) and to better read the incoming signal (nonCDR path). In addition, the HDMP-0452 may be configured as two 2:1 multiplexers or as two 1:2 buffers. The HDMP-0452 design allows for CDR placement at any location with respect to the hard disk slots. For example, if the BYPASS[0]- pin is floating and hard disk slots A to D are connected to PBC cells 1 to 4 respectively (see Figure 3), the CDR function will be performed before entering the hard disk at slot A. To obtain a CDR function after slot D (see Figure 4), BYPASS[1]- must be floating and hard disk slots A to D must be connected to PBC cells 2,3,4, and 0 respectively. Table 2 shows all possible connections. For configurations where the CDR is before slot A, a Signal Detect (SD) pin shows the status of the signal at the incoming cable. HDMP-0452 Block Diagram
CDR
training controls. It does this by continually frequency locking onto the 106.25 MHz reference clock (REFCLK) and then phase locking onto the input data stream. Once bit locked, the CDR generates a high-speed sampling clock. This clock is used to sample or repeat the incoming data to produce the CDR output. The CDR jitter specifications listed in this data sheet assume an input that has been 8B/10B encoded.
SD OUTPUT
Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If transmission lines are connected to the output pins, the lines should be differentially terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance.
EQU INPUT
The Signal Detect (SD) block detects if the incoming data on FM_NODE[0] is valid by examining the differential amplitude of that input. The incoming data is considered valid, and SD is driven high, as long as the amplitude is greater than 400 mV (differential peak-to-peak). SD is driven low as long as the amplitude of the input signal is less than 100 mV (differential peak-to-peak). When the amplitude of the input signal is between 100-400 mV (differential peak-to-peak), SD is unpredictable.
BLL OUTPUT
All FM_NODE[n] high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs.
BYPASS[N]- INPUT
The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking feature allows the CDR to lock onto the input data stream without external
All TO_NODE[n] high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL Outputs on the HDMP-0452 are of equal strength and can drive in excess of 120 inches of FR-4 PCB trace.
The active low BYPASS[n]- inputs control the data flow through the HDMP-0452. All BYPASS pins are LVTTL and contain internal pull-up circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1 k resistor. Otherwise, the BYPASS[n]- inputs should be left to float. In this case, the internal pull-up circuitry will force them high.
REFCLK INPUT
The LVTTL REFCLK input provides a reference oscillator for frequency acquisition of the CDR. The REFCLK frequency should be within 100 ppm of one-tenth of the incoming data rate in baud (106.25 MHz 100 ppm for FC-AL running at 1.0625 GBd).
2
FM_NODE[1]
FM_NODE[2]
FM_NODE[3]
FM_NODE[4]
TO_NODE[0]
BYPASS[2]-
BYPASS[3]-
BYPASS[4]-
FM_NODE[0]
TO_NODE[1]
TO_NODE[2]
TO_NODE[3]
TO_NODE[4]
BYPASS[1]-
BYPASS[0]-
SD
EQU BLL TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL BLL EQU TTL
SD
1 0
1 0
1 0
1 0
1 0
CDR
CPLL
TTL
REFCLK
Figure 1. Block diagram of HDMP-0452.
Table 1. Truth Table for CDR at Entry Configuration.
TO_LOOP FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] FM_NODE[4] TO_NODE[4] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_NODE[3] FM_NODE[3] FM_NODE[3] FM_NODE[3] TO_NODE[3] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] FM_LOOP FM_NODE[1] FM_NODE[2] FM_NODE[2] TO_NODE[2] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] FM_LOOP FM_NODE[1] TO_NODE[1] FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP FM_LOOP BYPASS[4]- 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BYPASS[3]- 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BYPASS[2]- 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BYPASS[1]- 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Note: FM_LOOP = FM_NODE[0], TO_LOOP = TO_NODE[0], BYPASS[0]- = 1.
Table 2. Pin Connection Diagram to Achieve Desired CDR Location (see Figures 3, 4). Hard Disks Connection to PBC Cells CDR Position (x) Cell Connected to Cable A BC D 1234 xA B C D 0 A BC D 0123 AxB C D 4 A BC D 4012 A BxC D 3 A BC D 3401 A B CxD 2 A BC D 2340 A B C Dx 1
Note: x denotes CDR position with respect to hard disks.
3
FM_NODE[2]+
FM_NODE[3]+
FM_NODE[2]-
44 43 42 41 40 39 38 37 36 35 34 GND VCC FM_NODE [1]- FM_NODE [1]+ VCCHS[1] TO_NODE [1]- TO_NODE [1]+ GND FM_NODE [0]- FM_NODE [0]+ GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 GND VCCA TO_NODE[4]+ TO_NODE[4]- VCCHS[4] FM_NODE[4]+ FM_NODE[4]- VCCHS[0] TO_NODE[0]- TO_NODE[0]+ GND
GND
FM_NODE[3]-
TO_NODE[2]+
TO_NODE[3]+
TO_NODE[2]-
TO_NODE[3]-
VCCHS[2]
VCCHS[3]
Agilent HDMP-0452
nnnn-nnn Rz.zz S YYWW
30 29 28 27 26 25 24 23
REFCLK
BYPASS[0]-
BYPASS[1]-
BYPASS[2]-
BYPASS[3]-
BYPASS[4]-
CPLL1
GND
SD
nnnn-nnn = WAFER LOT - BUILD NUMBER Rz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (ON BACK SIDE)
Figure 2. HDMP-0452 package layout and marking, top view.
I/O Type Definitions I/O Type I-LVTTL O-LVTTL HS_OUT HS_IN C S Definition LVTTL Input LVTTL Output High-Speed Output, LVPECL Compatible High-Speed Input External Circuit Node Power Supply or Ground
4
CPLL0
VCC
Table 3. Pin Definitions for HDMP-0452. Pin Name TO_NODE[0]+ TO_NODE[0]- TO_NODE[1]+ TO_NODE[1]- TO_NODE[2]+ TO_NODE[2]- TO_NODE[3]+ TO_NODE[3]- TO_NODE[4]+ TO_NODE[4]- FM_NODE[0]+ FM_NODE[0]- FM_NODE[1]+ FM_NODE[1]- FM_NODE[2]+ FM_NODE[2]- FM_NODE[3]+ FM_NODE[3]- FM_NODE[4]+ FM_NODE[4]- BYPASS[0]- BYPASS[1]- BYPASS[2]- BYPASS[3]- BYPASS[4]- REFCLK CPLL1 CPLL0 SD Pin 24 25 07 06 44 43 38 37 31 30 10 09 04 03 41 40 35 34 28 27 14 15 16 17 18 13 21 22 19 Pin Type Pin Description HS_OUT Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.
HS_IN
Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.
I-LVTTL
Bypass Inputs: For "disk bypassed" mode, connect BYPASS[n]- to GND through a 1 k resistor. For "disk in loop" mode, float HIGH.
I-LVTTL C
Reference Clock: A user-supplied clock reference used for frequency acquisition in the Clock and Data Recovery (CDR) circuit. Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1 F. Signal Detect: Indicates acceptable signal amplitude on the FM_NODE[0] inputs. If (FM_NODE[0]+ - FM_NODE[0]-) >= 400 mV peak-to-peak, SD = 1 If 400 mV > (FM_NODE[0]+ - FM_NODE[0]-) > 100 mV, SD = unpredictable If 100 mV >= (FM_NODE[0]+ - FM_NODE[0]-), SD = 0 Ground: Normally 0 volts. See Figure 11 for Recommended Power Supply Filtering.
O-LVTTL
GND
01 08 11 12 23 33 39 32
S
VCCA
S
Analog Power Supply: Normally 3.3 volts. Used to provide a clean supply line for the Clock and Data Recovery (CDR) circuit. See Figure 11 for Recommended Power Supply Filtering. High Speed Supply: Normally 3.3 volts. Used only for high-speed outputs (TO_NODE[n]). See Figure 11 for Recommended Power Supply Filtering.
VCCHS[0] VCCHS[1] VCCHS[2] VCCHS[3] VCCHS[4] VCC 5
26 05 42 36 29 02 20
S S S S S S
Logic Power Supply: Normally 3.3 volts. Used for internal logic. See Figure 11 for Recommended Power Supply Filtering.
6
TO_NODE[1] = TO_LOOP
TO_NODE[1]
1 1
SERDES
FM_NODE[1] = FM_LOOP
FM_NODE[1]
HARD DISK A
0
1
BYPASS[1]- = 1
BYPASS[1]-
1 0
TO_NODE[2]
TO_NODE[2]
SERDES
2 2
FM_NODE[2] BYPASS[2]-
0 1 0 1
HARD DISK A
HARD DISK B
SERDES
FM_NODE[2]
Figure 4. Connection diagram for CDR at last cell.
BYPASS[2]-
Figure 3. Connection diagram for CDR at first cell.
TO_NODE[3]
CDR
TO_NODE[3]
3
FM_NODE[3] BYPASS[3]-
HARD DISK B
CDR SERDES 0 1
HARD DISK C
3
FM_NODE[3] BYPASS[3]-
0 1
SERDES
TO_NODE[4]
TO_NODE[4]
SERDES
4
FM_NODE[4] BYPASS[4]-
0 1
4
FM_NODE[4]
HARD DISK C 0
HARD DISK D
SERDES
BYPASS[4]-
1
TO_NODE[0]
SERDES
0
FM_NODE[0] BYPASS[0]-
0 1
TO_NODE[0] = TO_LOOP
0
HARD DISK D 0
FM_NODE[0] = FM_LOOP BYPASS[0]- = 1
1
HDMP-0452 Absolute Maximum Ratings TA = 25C, except as specified. Operation in excess of any of these conditions may result in permanent damage to this device. Symbol VCC VIN,LVTTL VIN,HS_IN IO,LVTTL Tstg Tj Parameter Supply Voltage LVTTL Input Voltage HS_IN Input Voltage LVTTL Output Voltage Storage Temperature Junction Temperature Units V V V mA C C -65 0 Min. -0.7 -0.7 1.3 Max. 4.0 4.0 VCC 13 +150 +125
HDMP-0452 Guaranteed Operating Rates TA = 0C to +70C, VCC = 3.15 V to 3.45 V Serial Clock Rate FC (MBd) Min. Max. 1040 1080 Serial Clock Rate GE (MBd) Min. Max. 1240 1260
HDMP-0452 CDR Reference Clock Requirements TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol f Ftol Symm Parameter Nominal Frequency Frequency Tolerance Symmetry (Duty Cycle) Units MHz ppm % -100 40 Min. Typ. 106.25 +100 60 -100 40 Max. Min. Typ. 125.00 +100 60 Max.
HDMP-0452 DC Electrical Specifications TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol VIH,LVTTL VIL,LVTTL VOH,LVTTL VOL,LVTTL IIH,LVTTL IIL,LVTTL ICC Parameter LVTTL Input High Voltage Range LVTTL Input Low Voltage Range LVTTL Output High Voltage Range, IOH = -400 A LVTTL Output Low Voltage Level, IOL = 1 mA Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V Total Supply Current, TA = 25C Units V V V V A A mA Min. 2.0 0 2.2 0 0.003 300 200 Typ. Max. 4.0 0.8 3.45 0.6 40 600
7
HDMP-0452 AC Electrical Specifications TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol tdelay1 tdelay2 tr,LVTTLin tf,LVTTLin trs,HS_OUT tfs,HS_OUT trd,HS_OUT tfd,HS_OUT VIP,HS_IN VOP,HS_OUT Parameter Total Loop Latency from FM_NODE[0] to TO_NODE[0] Per Cell Latency from FM_NODE[4] to TO_NODE[0] Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V HS_OUT Single-Ended Rise Time, 20%-80% HS_OUT Single-Ended Fall Time, 20%-80% HS_OUT Differential Rise Time, 20%-80% HS_OUT Differential Fall Time, 20%-80% HS_IN Input Peak-to-Peak Required Differential Voltage Range HS_OUT Output Pk-Pk Diff. Voltage Range (Z0 = 75 Ohm, Fig. 9) Units ns ns ns ns ps ps ps ps mV mV 200 1100 Min. Typ. 4.0 0.8 2 2 200 200 200 200 1200 1400 350 350 350 350 2000 2000 Max.
HDMP-0452 Power Dissipation and Thermal Resistance TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol PD jc Parameter Power Dissipation Thermal Resistance, Junction to Case Units mW C/W Typ. 660 7 Max. 950
HDMP-0452 Output Jitter Characteristics TA = 0C to +70C, VCC = 3.15 V to 3.45 V Symbol RJ DJ Parameter Random Jitter at TO_NODE pins (1 sigma rms) Deterministic Jitter at TO_NODE pins (pk-pk) Units ps ps Typ. 5 20 Max.
Please refer to Figures 6 and 7 for jitter measurement setup information.
HDMP-0452 Locking Characteristics TA = 0C to +70C, VCC = 3.15 V to 3.45 V Parameter Bit Sync Time (phase lock) Frequency Lock at Powerup Units bits s Max. 2500 500
8
Figure 5. Eye diagram of FM_NODE[1] high-speed differential output. Note: Measurement taken with a 27-1 PRBS input to FM_NODE[0].
RANDOM JITTER
HP70841B PATTERN GENERATOR
HDMP-0452
DATA 2 BIAS TEE FM_NODE[0] BYPASS[0]- BYPASS[1:4]- REFCLK TO_NODE[0] 1 k N/C
K28.7
CLOCK
1062.5 MHz
1.4 V 2 106.25 MHz 1/10 CH 1/2 106.25 MHz TRIGGER
HP70311A CLOCK SOURCE
HP83480A DIGITAL COMMUNICATION ANALYZER
Figure 6. Setup for measurement of random jitter.
DETERMINISTIC JITTER
HP70841B PATTERN GENERATOR
HDMP-0452
DATA 2 BIAS TEE FM_NODE[0] BYPASS[0]- BYPASS[1:4]- REFCLK TO_NODE[0] 1 k N/C
+K28.5 -K28.5
CLOCK
1062.5 MHz
1.4 V 2 106.25 MHz 1/10 CH 1/2 106.25 MHz 1/2 53.125 MHz TRIGGER
HP70311A CLOCK SOURCE
HP83480A DIGITAL COMMUNICATION ANALYZER
Figure 7. Setup for measurement of deterministic jitter.
9
O_LVTTL
VCC
I_LVTTL
VCC
VCC
VBB 1.4 V
GND GND ESD PROTECTION ESD PROTECTION GND
Figure 8. O-LVTTL and I-LVTTL simplified circuit schematic.
HS_OUT
75 VCCHS VCC VCC
HS_IN
+ - VCC
+ -
TO_NODE[n]+
Z0 = 75
0.01 F
FM_NODE[n]+
2*Z0 = 150 TO_NODE[n]- Z0 = 75 GND ESD
PROTECTION
0.01 F
FM_NODE[n]- GND ESD
PROTECTION
GND
GND
NOTE: FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT.
Figure 9. HS_OUT and HS_IN simplified circuit schematic.
10
Package Information Item Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (Seating Plane) Details Plastic 85% Tin, 15% Lead 200-800 micro-inches 0.33 mm max. 0.10 mm max.
Mechanical Dimensions
PIN #1
HDMP-0452 TOP VIEW
E1
E
c
D1 D
b e L
0.25 GAUGE PLANE
A2
A
A1
SEATING PLANE
ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER E1/D1 HDMP-0452 TOLERANCE 10.00 E/D 13.20 b 0.35 e 0.80 L 0.88 c 0.23 A2 2.00 A1 0.25 A 2.45 MAX.
0.10 0.20 0.05 BASIC + 0.15/ MAX. + 0.10/ 0.25 - 0.10 - 0.05
Figure 10. HDMP-0452 package drawing.
11
Supply Filtering
VCC VCC GND
44 43 42 41 40 39 38 37 36 35 34 GND VCC 1 2 3 4 VCC 5 6 7 GND 8 9 10 GND 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 GND VCC
HDMP-0452
VCC
28 27 26 25 24 23 GND VCC
GND
CPLL1
NOTE: CAPACITORS = 0.1 F, RESISTORS = 10
Figure 11. Recommended power supply filtering.
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. September 28, 2001 5988-4333EN
VCC
CPLL0

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